A FET includes a source/drain region formed in or upon a wafer and a gate covering a channel region formed in or upon the wafer. A FET may be an nFET or a pFET and may be formed utilizing CMOS (Complementary metal-oxide-semiconductor) fabrication techniques.
The term FinFET typically refers to a nonplanar, double-gate transistor. Integrated circuits that include FinFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulator layer, e.g., a buried oxide layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET generally includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. At opposite ends of the fin body are heavily-doped source/drain regions.
FET fabrication techniques form various trenches. For example, in FinFET fabrication, numerous fins may be formed by etching or otherwise removing portions of one or more layer(s). The portions of the one or more layer(s) that are retained form the fins and the space between the fins is referred to as a fin trench. Similarly, in gate-last CMOS fabrication, a dummy gate is removed between opposing gate spacers and is replaced by a conductive replacement gate. The space between the opposing spacers subsequent to the removal of the dummy gate is referred to as a gate trench.